Currently, various applications, e.g., communication receivers and tuners, are being implemented such that they require analog-to-digital (A-D) converters which produce digital output samples or signals with a very high sampling rate and high effective number of bits (ENOB). For example, a receiver system based on the Data Over Cable Service Interface Specification (DOCSIS) standard may be implemented such that there is a need to support reception of up to 8 sets of 8-bonded 6 MHz channels across the operating frequency range of about 54 to 1004 MHz. A traditional approach includes implementing multiple analog tuners, however, such technique may be ineffective in terms of the resultant power and area requirements. Another approach may include implementing a wideband sampling tuner that supports the required operating frequency range.
Such a wideband sampling tuner is effectively a wideband A-D converter which, in this example, may be required to sample at a rate of 3 GS/sec (giga-samples per second), have an input bandwidth of 1 GHz and an ENOB of 10.5 bits minimum. Implementation of such a wideband A-D converter (with the above performance requirements) may be extremely challenging even using latest generation technologies (e.g., deep sub-micron technologies). Accordingly, such wideband high-sampling rate A-D converters are typically implemented as an array of time-interleaved A-D converters each having a lower sampling rate (e.g., a fraction of the sampling rate of the wideband A-D converter).
However, such arrangements that include time-interleaving outputs of an A-D converter array are well known to suffer from signal impairments due to DC (e.g., mean value) and gain (e.g., peak-to-peak value) imbalance between outputs of individual A-D converters of the array. Both DC and gain imbalance typically lead to an error in the sampled level, which in turn may lead to one or more spurious peaks being generated in the frequency domain, referred to as time interleaving errors.
Techniques that attempt to correct for such errors are generally based on running a calibration utility during, e.g., initialization process of the A-D converter array, or applying correction in the analog domain to correct DC and gain imbalance. However, such techniques have the disadvantage that there is no real time correction for calibration drift (e.g., for calibration or correction performed in the digital domain), and may have associated time and/or circuit overheads.